1. Field of the Invention
This invention relates to computer processors, and more particularly to using programmable logic devices (PLDs) for a bus controller, a clock generator and a wait state controller for a V33 microprocessor.
2. Description of Related Art
The V33 microprocessor is described in .mu.PD70136 (V33) 16-Bit Microprocessors: High-Speed, CMOS, a publication available from NEC Electronics Inc., 401 Ellis Street, P.O. Box 7241, Mountain View, Calif. 94039. The V33 microprocessor has an internal clock rate of up to 16 MHz. As shown in FIG. 1, the V33 microprocessor 1 has data lines D.sub.0 -D.sub.15 which carry data between microprocessor 1 and, say, circuitry 1000 which may contain memory, I/O and other devices. Microprocessor 1 also has address lines A.sub.0 -A.sub.23 which can be used, for example, to carry the address of a memory location in circuitry 1000 to which location data on D.sub.0 -D.sub.15 must be written by microprocessor 1 or from which location data must be driven onto D.sub.0 -D.sub.15 to be subsequently read by microprocessor 1. Microprocessor 1 also has status lines BUSST0, BUSST1, M/IO, R/W, UBE, BCYST, and DSTB. These lines inform circuitry 1000 of the state of microprocessor 1. For example, DSTB is asserted low by microprocessor 1 when microprocessor 1 writes data on D.sub.0 -D.sub.15 or ,reads data from D.sub.0 -D.sub.15. Thus DSTB can be used to signal circuitry 1000 when to start or stop reading data from D.sub.0 -D.sub.15 or writing data onto D.sub.0 -D.sub.15.
Signals on some of the lines of microprocessor 1 can be skewed. For example, when microprocessor 1 writes data onto D.sub.0 -D.sub.15, it may assert DSTB before the address lines A.sub.0 -A.sub.23 and the status lines BUSST0, BUSST1, M/IO, R/W, UBE and BCYST become valid. If circuitry 1000 starts reading data from D.sub.0 -D.sub.15 when DSTB gets asserted, circuitry 1000 may end up reading the data to a wrong address indicated by invalid lines A.sub.0 -A.sub.23. Also, when microprocessor 1 reads data from D.sub.0 -D.sub.15, it may deassert DSTB too soon, i.e. before it has actually finished reading. As a result, if circuitry 1000 stops driving data onto D.sub.0 -D.sub.15 when DSTB gets deasserted, microprocessor 1 might get wrong data from D.sub.0 -D.sub.15.
Such skewing of signals is not unique to the V33 microprocessor. It occurs in other fast computer processors. The problems caused by the skewing in other processors have been solved by using a bus controller. FIG. 2 shows a block diagram for such a solution. Microprocessor 900 is a fast microprocessor, such as, for example, a type 80286 available from Intel Corporation, Santa Clara, Calif. A circuitry 1001, like circuitry 1000 in FIG. 1, may contain memory, I/O, and other devices. Lines 990 include data and address lines of microprocessor 900. A bus controller 901 is a logic device which accepts, as input, status lines 991 from microprocessor 900 and, perhaps, some other signals (not shown), for example, a clock signal. Bus controller 901 produces control signals 992 which inform circuitry 1001 of the state of microprocessor 900 and which are free from skewing problems of lines 990 and 991. An example of bus controller 901 is the type 82288 controller described in 82288 Bus Controller for iAPX 286 Processors (INTEL Corporation, 1985). Also known in the prior art is a PLD programmed to perform as bus controller 901 for INTEL 80286. Unfortunately, these bus controllers cannot be used with a type V33 microprocessor because the status lines, address lines and data lines of the type 80286 microprocessor have different characteristics from those lines of the type V33 microprocessor. A bus controller for a V33 microprocessor has not been so far provided.
To cause V33 microprocessor 1, FIG. 1, to operate at 16 MHz, a 16 MHz clock signal (processor clock) must be provided on input CLK of microprocessor 1. A diagram of such a signal 47 is shown in FIG. 3. The signal 47 is used to synchronize the operation of microprocessor 1. That is to say, microprocessor 1 detects when the processor clock 47 is high (segment 63, FIG. 3), when it is low (segment 64), and when the transitions 65 between the high and low states occur, and microprocessor 1 performs some well-defined operations when the processor clock is high, some operations when the processor clock is low, some operations during the transitions from the low level to the high level (i.e. on the rising edge of the processor clock 47), and some operations during the transitions from the high level to the low level (on the falling edge of the processor clock 47).
A 16 MHz clock signal can be generated by an oscillator. FIG. 3 shows a diagram of such a signal 48. Unfortunately, the rising and falling edges 62 of the oscillator signal 48 can be too long to be used with microprocessor 1. Microprocessor 1 requires these edges to be at most 5 ns (parameters tKR, tKF in FIG. 3). The oscillator signal edges 62 can be much longer. However, circuits are known that "waveshape" oscillator signal 48 to produce a "square" wave, i.e. a signal with shorter rising and falling edges.
In some computer systems, some devices connected to a 16 MHz processor may have to be synchronized by a faster "system" clock, say a 32 MHz clock. Such computer systems comprising, say, a 16 MHz microprocessor V60 (.mu.PD70616) are well-known in the art. Microprocessor V60 is described in the .mu.PD70616(V60) data sheet, 1986, available from NEC. In such a computer system, a 16 MHz processor clock may be generated from a 32 MHz system clock by, say, an NEC chip .mu.PD71611 described in .mu.PD71611 CMOS Clock Generator, September 1986. FIG. 4 shows a block diagram of part of such a computer system. Chip 2025 is a 16 MHz clock generator .mu.PD71611. Chip 2025 accepts a 32 MHz system clock EXFS from another clock generator 2026. From system clock EXFS, chip 2025 generates a 16 MHz processor clock CLK for a V60 microprocessor 2001. System clock EXFS is also used to synchronize devices 2003. Chip 2025 also generates an 8MHz clock PRCLK (not shown) for synchronizing other devices (not shown) connected to microprocessor 2001. FIG. 3 shows a diagram of system clock 46 (EXFS) and processor clock 49 (CLK).
Unfortunately, there exists a significant skew between the clocks EXFS and CLK. In other words, as is seen from FIG. 3, there is a significant time difference between the edges of EXFS and CLK. The time interval tDCKL between the falling edge 66 of the system clock EXFS and the falling edge 68 of the processor clock CLK can be up to 20 ns. The time interval tDCKH between the falling edge 67 of the system clock EXFS and the rising edge 69 of the processor clock CLK can also be up to 20 ns. Some computer systems need that skew to be much smaller.
It should also be noted that chip 2025 is a customized, non-programmable chip.
A typical operation of microprocessor 1, such as reading data from memory or writing data to an I/O device, lasts one bus cycle. FIG. 5 shows a diagram of processor clock 47 (CLK) in a bus cycle. Each bus cycle starts on a falling edge of the processor clock 47 (point 85 in FIG. 5) and lasts for 2 or more periods of the clock 47 depending on how fast the memory or the I/O device is. Each such period of the clock 47 is called a bus state. The first bus state of a bus cycle is called T1, the second bus state T2. A bus cycle may consist of only two bus states--T1 and T2. Yet if a memory or I/O device needs more time to complete the operation, microprocessor 1 will insert additional bus states (called wait states) into the bus cycle. The bus cycle in FIG. 5 has 3 wait states--TW1, TW2 and TW3.
Devices connected to microprocessor 1, such as devices of circuitry 1000, inform microprocessor 1 that they are ready for the current bus cycle to terminate, by asserting the READY line of microprocessor 1 low. See FIG. 1. FIG. 5 shows a diagram of the READY signal 45 for a bus cycle with 3 wait states. Microprocessor 1 will sample its READY line at point 81 of T2, and since READY is high at that point, microprocessor 1 will insert the first wait state TW1. Microprocessor 1 will sample READY again at point 82 of TW1 and, seeing READY high, will insert another wait state, TW2. Microprocessor 1 will then sample READY at point 83 and, seeing READY high, will insert TW3. Microprocessor 1 will again sample READY at point 84. By this time, circuitry 1000 has asserted READY low, and microprocessor 1 will terminate the bus cycle. The next bus state will be T1 of the next bus cycle.
This way of terminating a bus cycle is not unique to the V33 microprocessor 1. V60 microprocessor 2001, FIG. 4, also has a READY line used similarly to the READY line of microprocessor 1. In prior art computer systems using the V60 microprocessor, it was found that READY generation could be simplified by using a wait state controller as shown in FIG. 4. Chip 2025, which acts as a clock generator for V60 microprocessor 2001, acts also as a wait state controller for microprocessor 2001. A device 2004 connected to chip 2000 does not itself assert the READY line of chip 2001. Instead the device 2004 provides on lines WAIT0, WAIT1, and WAIT2, the number of wait states which it wants to be inserted into the current bus cycle. This number can be any number between zero and seven. This number is provided to chip 2025 which asserts the READY line of microprocessor 2001 accordingly.
Unfortunately, chip 2025 is incompatible with V33.
Also, chip 2025 is not programmable.